Exemplary embodiments of the disclosure relate generally to a method of forming the conductive lines of a semiconductor memory device and, more particularly, to a method of forming the conductive lines of a semiconductor memory device using a metal silicide layer to improve the resistance of the conductive lines.
To lower the sheet resistance and the contact resistance of a semiconductor memory device, a metal silicide layer is used as a material for the conductive lines of the semiconductor memory device. Where the conductive lines of the semiconductor memory device are formed using the metal silicide layer, there is a problem in that a bridge phenomenon is generated in which the conductive lines are electrically coupled together.
FIGS. 1A and 1B are cross-sectional views showing a conventional method of forming conductive lines of a semiconductor memory device. In particular, FIGS. 1A and 1B show an example in which a metal silicide layer is used as the conductive lines of the semiconductor memory device.
Referring to FIG. 1A, a plurality of polysilicon patterns 15, insulated from each other with an insulating layer 17 interposed therebetween, is formed over an underlying layer 11. The polysilicon patterns 15 can be patterns that are used as word lines WL, a drain select line DSL, and a source select line SSL of a NAND flash memory device, for example.
For example, a case in which the polysilicon patterns 15 are used as the word lines WL, the drain select line DSL, and the source select line SSL is described below. The polysilicon patterns 15 can be formed using the following method, for example. First, a gate insulating layer 13 used as a dielectric layer is formed over a semiconductor substrate in which the underlying layer 11 (i.e., an isolation layer) is formed. A polysilicon layer is formed over the gate insulating layer 13. The polysilicon layer is patterned to form the plurality of separated polysilicon patterns 15. The gate insulating layer 13 can be patterned after the polysilicon patterns 15 are formed.
For reference, only the cross section taken along the underlying layer 11 (i.e., the isolation layer) is shown in FIG. 1. Although not shown, a gate insulating layer (not shown) used as a tunnel insulating layer, a floating gate (not shown), the gate insulating layer 13 used as the dielectric layer, and the polysilicon pattern 15 can be stacked over the active regions (not shown) of the semiconductor substrate separated by the underlying layer 11 (i.e., the isolation layer).
After the polysilicon patterns 15 are formed as described above, the insulating layer 17 for insulating between the polysilicon patterns 15 is formed with a height higher than a top surface of the polysilicon patterns 15. Thus, the space between the polysilicon patterns 15 is filled with the insulating layer 17. Next, the insulating layers 17 are polished to expose the top surface of the polysilicon patterns 15.
Referring to FIG. 1B, the top surface of the polysilicon patterns 15 is made to react with metal through a silicidation process, thereby forming metal silicide patterns 19 that are self-aligned over the silicon patterns 15. The metal silicidation process is described in detail below.
First, the height of the insulating layer 17 is lowered using an etch process, such as an etch-back process, thereby exposing upper sidewalls of the polysilicon patterns 15. After a cleaning process is performed, a metal layer is formed on the exposed surface of the polysilicon patterns 15 and a surface of the insulating layer 17. Next, a capping layer can be further formed over the metal layer.
After the metal layer is formed, a primary annealing process is performed. Thus, metal from the metal layer diffuses toward the polysilicon patterns 15 and an upper portion of the polysilicon patterns 15 is changed into metal silicide. Next, the unreacted metal layer that remains intact and the capping layer are removed. Accordingly, metal silicide patterns 19 having a first resistance are self-aligned on the polysilicon patterns 15. Next, a secondary annealing process is performed to form metal silicide patterns 19 (i.e., targets) having a second resistance lower than the first resistance. Accordingly, word lines WL, a drain select line DSL, and a source select line SSL, composed of stack structures of the polysilicon patterns 15 and the metal silicide patterns 19, are formed.
In the process of forming the metal silicide patterns 19, the metal silicide pattern 19 can be wider than the polysilicon pattern 15. In this case, since an interval I between conductive lines including the metal silicide patterns 19 is narrowed, a bridge phenomenon in which neighboring conductive lines are interconnected may be generated. The phenomenon becomes worse with the interval I decreasing because the degree of integration of semiconductor memory devices is increased.